1. Field of the Invention
The present invention relates to an integration type A/D converter (analog-to-digital converter). Further, the present invention relates to a semiconductor device including the A/D converter and an electronic device.
2. Description of the Related Art
The physical quantity of sound, light, heat, power, an electric field, and a magnetic field in the natural world can be expressed as an analog parameter. On the other hand, in the fields of measurement, control, communication, and the like, digitalization of data processing has been advanced. A digital camera or the like is a good example of consumer-electronic devices. When the physical quantity which is treated as the analog quantity originally is treated as the digital quantity, an A/D converter (an analog-to-digital converter, hereinafter referred to as an ADC) serves as an interface between analog data and digital data. That is, the ADC converts analog data to digital data. When various physical quantities as described above in the natural world are processed as data, the ADC is necessary in many cases. Therefore, the ADC can be applied to various fields and is very important.
There are various types of ADCs, typically, a successive-approximation type, a parallel-comparison type (also referred to as a flash type), a ΔΣ type (also referred to as a ΣΔ type), an integration type, and the like.
The integration type ADC has a low conversion rate compared to other types but a simple circuit configuration, and thus can be manufactured at low cost and is not easily influenced by noise. Therefore, the integration type ADC is used in noisy environment, for applications which do not require a high update rate, or the like.
The operating principle of a dual slope type ADC, which is one kind of integration type ADCs and often used, will be described with reference to FIGS. 2 and 3. FIG. 2 illustrates a main portion of a circuit constituting the dual slope type ADC. The dual slope type ADC includes an integrator 154 having an operational amplifier 151, a resistor 152, and a capacitor 153; a first switch 156 which initializes output potential Vout of the integrator 154; a second switch 158 which serves as a charging switch for inputting input potential Vin to the integrator 154; and a third switch 160 which serves as a discharging switch for inputting reference potential Vref into the integrator 154.
Note that “potential” denotes relative potential energy when electric potential energy of a grounded electric node is set to be 0 here. This is also applied to the following description. However, it is sufficient that potential at an electric node which is a reference of an entire circuit can be clearly determined. It is not always necessary to set ground potential to be 0, and the spirit of the present invention hereinafter described is not limited thereto, either.
Operation of the conventional dual slope type ADC illustrated in FIG. 2 will be described hereinafter. First, the first switch 156 is turned on to cause a short circuit between two terminals of the capacitor 153, and the integrator 154 is initialized so that output potential Vout becomes offset potential Voffset. Next, the first switch 156 is turned off and then the second switch 158 is turned on, and input signals are accumulated in the integrator 154 for a certain period of time, so that electric power is stored there. Finally, the second switch 158 is turned off and then the third switch 160 is turned on, and electric power is released so that the output potential Vout of the integrator 154 returns to a level in initialization, i.e., the offset potential Voffset. By counting a period for discharge (discharging period), A/D conversion can be performed.
The discharging period is counted as follows: a count-up operation is started at a time when the third switch 160 is turned on, and the count-up operation is finished at a time when the output potential Vout is equal to the offset potential Voffset. Known counter circuits may be used for the count-up operation. Since the count-up operation is started at 0, a value obtained by multiplying digital data stored in the counter circuit in completion of the count-up operation by a clock cycle becomes a discharging period. That is, reset signals and clock signals for a certain period of time are used to control the counter circuit. In addition, in order to detect a point at which the output potential Vout is equal to the offset potential Voffset, a known comparator circuit which is not illustrated here may be used. That is, the output potential Vout is input to one of two input terminals of the comparator circuit and the offset potential Voffset is input to the other. Besides, a known circuit which combines logical gates may be used to control the first to third switches.
FIG. 3 shows a change of the output potential Vout of the integrator 154 with time. The x axis represents time and the y axis represents the output potential Vout of the integrator 154. In this case, the case is shown in which input voltage Vin1 (a difference between the input potential Vin and the offset potential Voffset) and input voltage Vin2 which is twice as large as Vin1 (a difference between the input potential Vin and the offset potential Voffset) are input. The output potential Vout of the integrator 154 at a start of the charging period T1 is equal to the offset potential Voffset regardless of a value of the input voltage Vin1 or the input voltage Vin2. In the charging period T1, the output potential Vout of the integrator 154 changes in accordance with a level of the input voltage Vin1 or the input voltage Vin2 in a linear manner. Therefore, output voltage Vout1 (a difference between the output potential Vout and the offset potential Voffset) and output voltage Vout2 (a difference between the output potential Vout and the offset potential Voffset) of the integrator 154 in completion of the charging period T1 have a level which has changed in accordance with the input voltage Vin1 or the input voltage Vin2 in a linear manner. Next, reference voltage having opposite polarity to the input voltage Vin1 or the input voltage Vin2 is input to the integrator 154, so that the output potential Vout of the integrator 154 is changed with a slope of opposite polarity to that in charging. At this time, since the reference voltage is constant, a slope of the output potential Vout changing with time is constant regardless of the input voltage Vin1 or the input voltage Vin2 in charging. As a result, a period T21 or a period T22, which is required until the output potential Vout of the integrator 154 returns to a level in initialization, is varied in accordance with a level of the input voltage Vin1 or the input voltage Vin2 in a linear manner.
Note that in the example of FIG. 2, when the input voltage is Vin1, the output voltage and the discharging period are Vout1 and T21, respectively. Further, when the input voltage is Vin2, the output voltage and the discharging period are Vout2 and T22, respectively.
In general, the following equation (1) is obtained using the charging period T1, the discharging period T2, the input potential Vin, the reference potential Vref, and the offset potential Voffset.(Vin−Voffset)*T1+(Vref−Voffset)*T2=0  (1)
Note that the integration type ADC is generally operated under the condition of Voffset=0, Vin>0, and Vref<0. However, the present invention is not limited thereto as long as (Vin−Voffset) and (Vref−Voffset) have opposite polarity, i.e., (Vin−Voffset)>0 and (Vref−Voffset)<0, or (Vin−Voffset)<0 and (Vref−Voffset)>0.
In order to operate the integration type ADC normally, it is necessary that the integrator 154 inside the ADC operates correctly. Specifically, the condition under which the output potential Vout of the integrator 154 is not saturated during operation is a condition under which the integration type ADC operates normally. That is, the condition under which the integration type ADC operates normally can be expressed by the following equation (2).
                                                                                  (                                                      V                    in                                    -                                      V                    offset                                                  )                            *                              T                1                                                    R              *              C                                                <                                                      V              limit                        -                          V              offset                                                                    (        2        )            
In the above equation, R represents resistance of the resistor 152 included in the integrator 154, C represents capacitance of the capacitor 153 included in the integrator 154, Vlimit represents the limit of the output potential which can operate the integrator 154 correctly, the left-hand side of the equation represents a change in output potential Vout of the integrator 154 in the charging period T1, and the right-hand side represents a range of a change in output potential Vout of the integrator 154. In the case of Vin>Voffset, Vlimit<Voffset, and Vlimit represents the lower limit of the output potential in the range in which the integrator 154 can be operated correctly. Hereinafter, the case of Vin>Voffset will be described but the description also applies to the case of Vin<Voffset.
When the equation (2) is solved for Vin, the following equation (3) is obtained.
                              V          offset                <                  V          in                <                                                            (                                                      V                    offset                                    -                                      V                    limit                                                  )                            *              R              *              C                                      T              1                                +                      V            offset                                              (        3        )            
In the equation (3), the range of values of the input potential Vin (hereinafter referred to as a dynamic range) is limited by various parameters which determine the operation of the integrator. Accordingly, various methods have been provided to enlarge the dynamic range (e.g., Reference 1: Japanese Patent No. 3100457 and Reference 2: Japanese Patent No. 2550889).